The invention relates to a method for planarization of semiconductor structures which have dielectric isolation regions. More particularly, the invention relates to a method for planarizing an organic polyimide layer during filling of deep trenches in a semiconductor substrate having low and high trench density regions with this material.
The present trend in semiconductor microelectronics technology is toward very large scale and ultra large scale integration (VLSI and ULSI, respectively) of microelectronic devices. Minimum device feature size approaching 1.0 .mu.m is the near term goal in this technology. In the fabrication of such integrated circuits one of the most favorite dielectric isolation scheme by which one region of the semiconductor substrate containing an active and/or passive device is electrically isolated from another is the trench isolation. In an embodiment thereof, deep trenches are made in the substrate by reactive ion etching. The trenches are typically about 5-6 .mu.m deep, about 2-3 .mu.m wide and spaced about 2.5.-3.5 .mu.m apart from another trench. During the etching of the trenches, the remaining semiconductor substrate is protected by a protective layer, typically consisting of silicon dioxide-silicon nitride sandwich structure. Following the forming of the trenches, they are filled with a suitable material such as oxide, polysilicon or an organic polymeric material, for example, polyimide.
While the dielectric-filled trench isolation provides effective dieletric isolation between devices, the fundamental disadvantage of this scheme is that the resulting structure tends to be nonplanar. To elaborate on this, attention is focussed on the polyimide-filled trench isolation. In this process, after etching the trench in the semiconductor substrate polyimide is applied over the entire substrate followed by a baking step to cure and evaporate the solvents in the polyimide. During this baking step since the trench bed offers a significantly greater volume to be filled with the polyimide material than the remainder of the substrate, invariably a trough is formed over the trench region. In other words, a difference in polyimide planarization or a "planarization delta" occurs in the polyimide material overlying the trench region and the remainder of the substrate.
In addition to this lack of complete local planarization, the prior art polyimide-filled trench isolation also suffers from lack of global planarization (i.e., planarization across the entire chip or wafer). To expound on this, it is not uncommon for a VLSI or ULSI chip to consist of high device density regions corresponding to a memory section having a large number (10,000 or more) of active devices (e.g., transistors) coexisting with low device density regions corresponding to a logic section or a test device area, the latter, in general, being the kerf area of the semiconductor wafer from which the chips are diced. Since each of the devices is surrounded with trench isolation, there will exist on the chip both high trench density and low trench density regions. When such a structure is coated with polyimide material since the high trench density region offers a significantly larger volume to be filled by polyimide compared to the low trench density region, a profoundly nonplanar polyimide-coated structure will result. That is, the thickness of the polyimide layer formed in the low trench density region will be significantly higher than that in the high trench density region. This situation is illustrated in FIG. 1 wherein 10 designates a single semiconductor substrate, shown as a broken piece, consisting of the high and low trench density regions 12 and 14, respectively. Illustratively, region 12 contains a plurality of polyimide-filled trenches 16--16 and region 14 contains a single polyimide-filled trench 18. .DELTA. in FIG. 1 designates the global planarization delta or the difference in thickness of the polyimide coatings 20 and 22 in the high and low trench density regions, respectively. Also shown in FIG. 1 is the local planarization delta designated by .delta. which was discussed hereinabove. While the actual values of .DELTA. and .delta. are governed by such factors as the high/low trench density, and relative separation of the trenches, .DELTA. and .delta. are typically in the ranges of approximately 1-2 .mu.m and 0.2-0.4 .mu.m, respectively.
The nonplanar polyimide-filled trench structures although provide an effective dielectric isolation between devices, pose a number disadvantages to subsequently forming single- or multi-level metallization to interconnect the various components of the integrated circuit. One disadvantage is that the uneven topology poses resolution problems in defining images thereon. Specifically, in the subtractive metallization process in which a blanket layer of metal is applied to the full surface of the substrate, followed by applying a photoresist layer to the resulting nonplanar metal surface and exposing to light for patterning the resist, the resolution of the image in the high and low trench density regions will not be the same. Consequently, the metallization pattern obtained by etching the blanket metal layer using this resist pattern as a mask will not have the desired line width, line spacing, etc. over the entire pattern, thereby having a direct bearing on the yield and reliability of the electronic components thus produced. Similar problems occur with respect to the additive metallization or lift-off process which was described and claimed for the first time in U.S. Pat. No. 2,559,389.
Another disadvantage of the nonplanar surface is that when a metal layer is applied over this surface, the resultant layer becomes thinner in those portions in which the underlying polyimide layer has a sharp gradient. These thinned down portions result in current crowding and possible failure due to electromigration. Yet another disadvantage of the nonplanar surface, particularly in the context of multilevel metallization where one level of metallization is insulated from the other by means of an insulative layer such as polyimide or quartz, is electrical shorting between one metallization level and the next due to formation of a thinner insulative layer in the high trench density regions.
Thus, when continued miniaturization of integrated circuits and increasing density imposing severe requirements on the width and spacing of the metallization patterns, planarity of the surface upon which the metallization system can be established has become a basic necessity. It is, therefore, very important that the substrate containing dielectrically isolated devices be as planar as possible for the overlying single- and multi-level metal pattern structure. The device structure requirements of the present integrated circuits are such that global planarization must be achieved within .+-. 0.3 .mu.m of the nominal fill level over all combinations of trench pattern factors.
Attempts have been made in the prior art to achieve planarization of a nonplanar surface. One such technique involves first etching the nonplanar polyimide-filled trench structure to reduce the thickness of the thicker polyimide layer in the low trench density region. Then, a series of steps including coating a thin layer of polyimide over the shallow surface regions followed by reflow, bake and etchback of the newly applied polyimide are accomplished. Next, these series of steps are repeated at least two times until the desired degree of planarization is obtained over the entire substrate. The basic drawback of this process is that it requires complex and multiple series of steps which are unsuitable for a high volume manufacturing environment particularly since the end results of the process are not satisfactory in terms of obtaining a totally planarized and defect-free structure.
"Dielectric Isolation planarization" by T. A. Bartush et al. IBM Technical Disclosure Bulletin, Vol. 21, No. 5, pp. 1868-1869, October 1978 discloses a method of planarizing an oxide-filled trench structure using photoresist masking step to selectively fill the pockets in the conformal oxide layer over the trenches. The photoresist is formed in the pockets by the block-off mask technique, followed by baking the resist to render it insoluble to a photoresist overcoat that is subsequently applied. By reactive ion etching the composite photoresist-oxide layers the structure is planarized.
"Forming Wide Trench Dielectric Isolation" by P. J. Tsang, IBM Technical Disclosure Bulletin Vol. 25, 11B, pp 6129-6130, April 1983 discloses a method in which both deep and narrow trenches are filled with oxide and planarized at the same time. In this method a hardened photoresist plug is provided in the trench pocket which is then used to facilitate the surface planarization somewhat analogous to the IBM TDB by Bartush et al.
U.S. Pat. No. 4,404,735 issued to J. Sakurai discloses a method of filling a trench in a silicon substrate by forming a glass or silicon layer followed by irradiating the layer with a laser beam to fluidify and flow into the trench gaps. Planar trench isolation so achieved in highly local but not global.
U.S. Pat. No. 4,389,281 issued to N. G. Anantha et al and assigned to the present assignee discloses a method for planarizing a non-uniform oxide formed over an oxide-filled trench. The oxide is removed by a planarizing resist-etching process so that etching in thicker resist areas proceeds at a rate slower than etching in thinner resist areas. In other words, planarization is achieved by taking advantage of the etch rate differences of materials.
U.S. Pat. No. 4,025,411 issued to Y. Hom-Ma et al discloses a plarization technique where a substrate is covered with a material having an etch rate approximately the same as that of the material which is to be etched, whereafter physical etching such as RF sputtering is conducted until the desired substrate is etched.
U.S. Pat. No. 4,073,054 issued to T. Kaji et al discloses a method similar to Hom-Ma et al discussed above except that two dielectric materials (oxide and polyimide) are used, the second dielectric material having the same etch rate as the first. The two dielectrics are then etched to form a locally planar surface.
U.S. Pat. No. 4,284,659 issued to J. Jaccodine et al discloses forming an interlevel glass layer having feed-through apertures on a partially completed semiconductor device. By means of CW laser the glass is caused to reflow and form a smooth topography about the apertures. Global planarization cannot be achieved by this process since the viscosity of the glass is rather too high to enable it to flow across the dimensions of the chip.
Japanese publication No. 58-138059 by H. Harada discloses filling a silicon trench with polyimide. Local trench-fill planarization is achieved by etching off excess polyimide.
U.S. Pat. No. 4,076,860 issued to H. Kuroda discloses a planarization technique involving the use of two photoresist layers in the context of forming electrode wirings in semiconductor devices. In this technique a combination of photolithographic exposures and plasma etching is utilized to planarize.
Thus, the prior art basically addresses the local planarization problem. None of the solutions with respect to local planarization is extendable to achieve global planarization. To the extent the prior art attempted to solve the global planarization problem, the provided solutions invariably involve multiple masking, coating and etching processes which are not only cumbersome, but unsuitable for manufacturing environment due to the high cost and unreliability associated therewith.
Accordingly, it is an object of the invention to provide a simple, straight forward and reliable process which enables global planarization over an entire semiconductor chip or wafer.
It is another object of the invention to achieve global planarization within .+-.0.3 .mu.m of the nominal fill regardless the nature of the polyimide-filled trench pattern.
The above ojects and other related objects and advantages may be achieved through the photoresist blockouts, block reflow and reflow enhancement via a wetting film of photoresist.